BBT3420 Datasheet, PDF (10/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
Opern
Read
Write
Opern
Addrs
Write
Read
Read Inc
PRE
1....1
1....1
PRE
1....1
1....1
1....1
1....1
TABLE 3-4. MDIO MANAGEMENT FRAME FORMATS
Clause 22 Format (from Table 22-10 in IEEE Std 802.3-2002)
ST
OP
PHYAD
REGAD
TA
DATA
01
10
PPPPP
RRRRR
Z0
DDDDDDDDDDDDDDDD
01
01
PPPPP
RRRRR
10
DDDDDDDDDDDDDDDD
Clause 45 Format (from Table 45-64 in IEEE 802.3.ae-2002)
ST
OP
PRTAD
DEVAD
TA
ADDRESS/DATA
00
00
PPPPP
DDDDD
10
AAAAAAAAAAAAAAAA
00
01
PPPPP
DDDDD
10
DDDDDDDDDDDDDDDD
00
11
PPPPP
DDDDD
Z0
DDDDDDDDDDDDDDDD
00
10
PPPPP
DDDDD
Z0
DDDDDDDDDDDDDDDD
IDLE
Z
Z
IDLE
Z
Z
Z
Z
3.11 Serial Management Interface
The BBT3420 implements both the Management Interface
defined in IEEE 802.3 Clause 22, and that defined in Clause
45. This two-pin interface allows serial read/write of the
internal control registers and consists of the MDC clock and
MDIO data terminals. The PADR[4..0] pins are used to select
the address to which a given BBT3420 device responds.
The remainder of the MDIO frame and access details
depend on the respective formats. The BBT3420
automatically detects which format is being used on a frame-
by-frame basis, based on the second START bit. The two
formats are shown in Table 3-4, together with the references
to the respective IEEE 802.3 specifications. The fields are as
follows:
• PRE, the Preamble field: at least 32 consecutive ‘1’ bits.
The BBT3420 will accept any number ≥32.
• ST, the Start of Frame; for Clause 22, <01>; for Clause 45,
<00>.
• OP, the Operation code; for Clause 22, Read and Write
operations are defined, all other values are invalid; for
Clause 45, additional operations to send the 16-bit
(indirect) register address, and to read data and (then)
increment the stored address are added.
• PHYAD/PRTAD; the PHYsical (Clause 22) or PoRT
(Clause 45) hardware ADdress; this 5-bit address must
match the PADR pins on the BBT3420.
• REGAD, REGister ADdress (Clause 22); this 5-bit address
specifies the register address. Replaced by the 16-bit
address value in Clause 45 format.
• DEVAD, DEVice ADdress (Clause 45); this 5-bit address
specifies which MMD at any given port is being
addressed. See Table 3-5 and section 3.13 for the
possible values the BBT3420 will respond to.
• TA, the TurnAround; allows time to avoid contention for a
read operation on the MDIO line.
• DATA; the 16 bit data values to be written to or being read
from the BBT3420.
• ADDRESS (Clause 45); this 16-bit address specifies the
register address for subsequent Clause 45 read or write
operations. A Read Increment operation will post-
increment the value.
• IDLE; this condition flags the end of the frame. Since the
IEEE specification calls for a pullup on the MDIO line, this
effectively provides the MMD with a ‘1’ character, which
can be the beginning of the next PREamble.
TABLE 3-5. DEVAD DEVICE ADDRESS SETUP TABLE
MFD
MFC
DEVAD
VALUE
IEEE
DEFAULT DEFINITION
1
1 DEVAD = 5
11’b DTE XS (XGXS
(000101’b)
Device)
1
0 DEVAD = 4
(00100’b)
PHY XS (XGXS
Device)
0
1 DEVAD = 31
(11111’b)
Vendor Specific
0
0 DEVAD = 30
(11110’b)
Vendor Specific
3.12 Clause 22 PHY Addressing
The PADR[4..0] hardware address pins control the PHYAD
value, allowing use of up to 31 BBT3420 (or other
compatible) devices on any MDC/MDIO line pair. Each
device may contain up to 32 registers, some of which are
defined by the IEEE standard, the others being Vendor-
defined. The Clause 22-accessible registers are listed in
Table 3-6.
3.13 Clause 45 PHY Addressing
The PADR[4..0] hardware address pins control the PRTAD
(Port Address) value, each port normally consisting of a
series of MDIO Managed Devices (MMDs). Each of the up to
31 Ports may include up to 31 different devices, of which the
current specification defines 6 types, and allows vendor
specification of two others. The native-mode BBT3420
corresponds to two of the defined types; it can be either a
PHY XS (DEVAD = 4) or a DTE XS (DEVAD = 5), but may
also be used as part of another defined type, or as a
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