BBT3420 Datasheet, PDF (7/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
control symbols, including the /K/ IDLE. Any proprietary
encoding scheme used should either incorporate these
codes, or arrange byte alignment differently. Comma
disparity action can be controlled via the CDET bits. Upon
detection of a comma, the Byte Alignment Unit shifts the
incoming data to align the received data properly in the 10-
bit character field. Two possible algorithms may be used for
byte alignment. The default is to byte-align on any comma
pattern. Although quick to align, and normally very reliable,
this method is susceptible to realignment on certain single-
bit errors or on successive K28.7 characters. The alternative
algorithm is that specified in the IEEE802.3ae-2002 clause
48 specification, and is much less susceptible to error.
Algorithm selection is controlled via MDIO register bit
PCS_SYNC_EN at address 1D’h (Clause 22, Table 3-28)
and/or C000’h (Clause 45, Table 3-32), unless overridden by
the XAUI_EN bit in the same registers. The recovered
receive clocks may be stretched (never slivered) during byte
alignment, but up to a full code group may be deleted or
modified while aligning the "comma" code group correctly to
the edges of the RefClock.
3.7.5 Data Decoding
The serial bit stream must be ordered "abcdeifghj" with "a"
being the first bit received and "j" the last. With the 10b/8b
XGMII decoder enabled, the decoded data is ordered
"ABCDEFGHK" with "A" being the LSB. The decoding of
valid 10b patterns is shown in Table 3-3 below. If the
TRANS_EN bit or XAUI_EN bit (the MDIO Registers at
Clause 22 addresses 10’h and 1D’h, see Table 3-15 and
Table 3-28), and/or Clause 45 address C001’h, see Table 3-
33) are set, all incoming XAUI IDLE patterns will be
converted to the XGMII IDLE pattern set by the control
register at address 1B’h (Clause 22 format) and/or C003’h
(Clause 45 format), with a default value 107’h, the standard
XGMII IDLE code (see Table 3-26). If neither bit is set, the
incoming IDLE codes will all be decoded to the appropriate
XGMII control code values. The first full column of IDLEs
after any column containing a non-IDLE will be stored in the
elasticity FIFO, and all subsequent full IDLE columns will
repeat this pattern, until another column containing a non-
IDLE is received.
If the BBT3420 XAUI_EN bit is set or the PCS_SYNC_EN
and DSKW_SM_EN bits are set, and the device has
detected a ‘Local Fault’ (see Table 3-10, Table 3-14, Table 3-
28 and/or Table 3-32 & Table 3-33), the XGMII output will
consist of the Sequence control character in channel A
(XAUI lane 0) and data characters of 0x00 in channels B & C
(lanes 1 and 2) plus a data character of 0x01 in channel D
(lane 3), the IEEE-defined ||LF|| Sequence Ordered_Set.
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