HFA3860 Datasheet, PDF (8/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
TXCLK
TX_PE
TXD
TX_RDY
FIRST DATA BIT SAMPLED
LSB DATA PACKET
MSB
LAST DATA BIT SAMPLED
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3860
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK.
FIGURE 4. TX PORT TIMING
RXCLK
RX_PE
MD_RDY
HEADER
FIELDS
PROCESSING
PREAMBLE/HEADER
MPDU DATA
RXD
LSB
DATA
MSB
NOTE: MD_RDY active after CRC16. See detailed timing diagrams on page 35.
FIGURE 5. RX PORT TIMING
RX Port
The timing diagram Figure 5 illustrates the relationships
between the various signals of the RX port. The receive data
port serially outputs the demodulated data from RXD. The
data is output as soon as it is demodulated by the HFA3860.
RX_PE must be at its active state throughout the receive
operation. When RX_PE is inactive the device's receive
functions, including acquisition, will be in a stand by mode.
RXCLK is an output from the HFA3860 and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3860 and it may be set to go active after SFD
or CRC fields. Note that RXCLK becomes active after the
Start Frame Delimiter (SFD) to clock out the Signal,
Service, and Length fields, then goes inactive during the
header CRC field. RXCLK becomes active again for the
MPDU. MD_RDY returns to its inactive state after RX_PE is
deactivated by the external controller, or if a header error is
detected. A header error is either a failure of the CRC
check, or the failure of the received signal field to match
one of the 4 programmed signal fields. For either type of
header error, the HFA3860 will reset itself after reception of
the CRC field. If MD_RDY had been set to go active after
CRC, it will remain low.
MD_RDY and RXCLK can be configured through CR 1, bit 6-7
to be active low, or active high. The receive port is completely
independent from the operation of the other interface ports
including the TX port, supporting therefore a full duplex mode.
I/Q A/D Interface
The PRISM baseband processor chip (HFA3860) includes
two 3-bit Analog to Digital converters (A/Ds) that sample the
analog input from the IF down converter. The I/Q A/D clock,
samples at twice the chip rate. The nominal sampling rate is
22MHz.
The interface specifications for the I and Q A/Ds are listed in
Table 2.
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