HFA3860 Datasheet, PDF(27/40 Page) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HFA3860 Datasheet, PDF (27/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

◁

HFA3860

TABLE 11. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION (Continued)

CONFIGURATION

NAME

TYPE

ADDRESS HEX 1/2/5.5/11 MBps

CR24

RX Status

CR25

RX service Field Status

CR26

RX Length Field status (high)

CR27

RX Length Field status (low)

CR28

Test Bus Address

R/W

CR29

Test Bus Monitor

CR30

Test Register 1

R/W

CR31

Test Register 2

R/W

Control Registers

The following tables describe the function of each control register along with the associated bits in each control register.

Bit 7:4

Bit 3:0

CONFIGURATION REGISTER 0 ADDRESS (0h) PART/VERSION CODE

Part Code

0 = HFA3860

Version Code

1 = First Version

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIGURATION REGISTER 1 ADDRESS (04h) I/O POLARITY

This register is used to define the phase of clocks and other interface signals. 00h is normal setting.

This controls the phase of the RX_CLK output

Logic 1 = Invert Clk

Logic 0 = Non-Inverted Clk

This control bit selects the active level of the MD_RDY output pin 34.

Logic 1 = MD_RDY is Active 0

Logic 0 = MD_RDY is Active 1

This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.

Logic 1 = CCA Active 1

Logic 0 = CCA Active 0

This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 44.

Logic 1 = ED Active 0

Logic 0 = ED Active 1

This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin 45.

Logic 1 = CRS Active 0

Logic 0 = CRS Active 1

This control bit selects the active level of the transmit enable (TX_PE) input pin 2.

Logic 1 = TX_PE Active 0

Logic 0 = TX_PE Active 1

This control bit selects the phase of the transmit output clock (TXCLK) pin 4.

Logic 1 = Inverted TXCLK

Logic 0 = NON-Inverted TXCLK

This control bit selects the active level of the transmit ready (TX_RDY) output pin 5.

Logic 1 = TX_RDY active 0

Logic 0 = TX_RDY active 1

4-27

▷