HFA3860 Datasheet, PDF (12/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
Definitions
ED. Energy Detect, indicates that the RSSI value exceeds its
programmed threshold.
CRS. Carrier Sense, indicates that a signal has been acquired
(PN acquisition).
TXCLK. Transmit clock.
Track. Indicates start of tracking and start of SFD time-out.
SFD Detect. Variable time after track starts.
Signal Field Ready. ~ 8µs after SFD detect.
Length Field Ready. ~ 32µs after SFD detect.
Header CRC Valid. ~ 48µs after SFD detect.
DCLK. Data bit clock.
FrqReg. Contents of the NCO frequency register.
PhaseReg. phase of signal after carrier loop correction.
NCO PhaseAccumReg. Contents of the NCO phase accu-
mulation register.
SQ1. Signal Quality measure #1. Contents of the bit sync
accumulator. Eight MSBs of most recent 16-bit stored value.
SQ2. Signal Quality measure #2. Signal phase variance
after removal of data, Eight MSBs of most recent 16-bit
stored value.
Sample CLK. Receive clock (RX sample clock). Nominally
22MHz.
Subsample CLK. LO rate symbol clock. Nominally 1MHz.
BitSyncAccum. Real time monitor of the bit synchronization
accumulator contents, mantissa only.
A/D_Cal_ck. Clock for applying A/D calibration corrections.
A/DCal. 5-bit value that drives the D/A adjusting the A/D
reference.
Power Down Modes
The power consumption modes of the HFA3860 are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 33), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 2), which disables the
transmitter when inactive.
Reset (RESET, pin 28), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a maximum
of 10µs before the device is back at its operational mode. It
also requires that RX_PE be activated briefly to clock in the
change of state.
The contents of the Configuration Registers are not effected
by any of the power down modes. The external processor
does have access and can modify any of the CRs during the
power down modes. No reconfiguration is required when
returning to operational modes.
Table 6 describes the power down modes available for the
HFA3860 (V_CC = 3.3V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
Transmitter Description
The HFA3860 transmitter is designed as a Direct Sequence
Spread Spectrum Phase Shift Keying (DSSS PSK)
modulator. It can handle data rates of up to 11 Mbps (refer to
AC and DC specifications). The various modes of the
modulator are Differential Binary Phase Shift Keying
(DBPSK), Differential Quaternary Phase Shift Keying
(DQPSK), Binary M-ary Bi-Orthogonal Keying (BMBOK),
and Quaternary M-ary Bi-Orthogonal Keying (QMBOK).
These implement data rates of 1, 2, 5.5 and 11 Mbps as
shown in Figure 8. The major functional blocks of the
transmitter include a network processor interface, DPSK
modulator, high rate modulator, a data scrambler and a
spreader, as shown on Figure 8. A description of (M-ARY)
Bi-Orthogonal Keying can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing.
The preamble and header are always transmitted as DBPSK
waveforms while the data packets can be configured to be
either DBPSK, DQPSK, BMBOK, or QMBOK. The preamble
is used by the receiver to achieve initial PN synchronization
while the header includes the necessary data fields of the
communications protocol to establish the physical layer link.
The transmitter generates the synchronization preamble and
header and knows when to make the DBPSK to DQPSK or
B/QMBOK switchover, as required.
For the PSK modes, the transmitter accepts data from the
external source, scrambles it, differentially encodes it as
either DBPSK or DQPSK, and mixes it with the BPSK PN
spreading. The baseband digital signals are then output to
the external IF modulator.
For the MBOK modes, the transmitter inputs the data and
forms it into nibbles (4 bits). At 5.5 Mbps, it selects one of 8
spread sequences from a table of sequences with 3 of those
bits and then picks the true or inverted version of that
sequence with the remaining bit. Thus, there are 16 possible
spread sequences to send, but only one is sent. This
sequence is then modulated on both the I and Q outputs.
The phase of the last bit of the header is used as an
absolute phase reference for the data portion of the packet.
At 11 Mbps, two nibbles are used, and each one is used as
above independently. One of the resulting sequences is
modulated on the I Channel and the other on the Q Channel
output. with 16 possible sequences on I and another 16
independently on Q, the total possible number of
combinations is 256. Of these only one is sent.
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