HFA3860 Datasheet, PDF (32/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS
Supplies address for test pin outputs and Test Bus Monitor Register
Bits 7:0
Test Bus Address = 00h
Quiet Test Bus
Test 7:0 = 00
TEST_CLK = 0
Bits 7:0
Test Bus Address = 01h
RX Acquisition Monitor These bits sequentially go high as the signal is input. Transitions are aligned to chip boundaries.
Bits are reset after last chip of message.
Test 7 = A/DCal (Full Scale)
Test 6 = CRS, Carrier Sense
Test 5 = ED, energy detect comparator output
Test 4 = Track, indicates start of tracking and start of SFD time-out
Test 3 = SFD Detect, variable time after track start
Test 2 = Signal Field Ready, ~ 8µs after SFD Detect
Test 1 = Length Field Ready, ~ 32µs after SFD Detect
Test 0 = Header CRC Valid, ~ 48µs after SFD Detect
TEST_CLK = Initial Detect
Bits 7:0
Test Bus Address = 02h
TX Field Monitor. These bits sequentially go high as the signal is output. Transitions are aligned to chip boundaries. Bits
are reset after last chip of valid message.
Test 7 = A/DCal (Full Scale)
Test 6 = TXPE Internal, Inactive edge of pad TXPE delayed
Test 5 = Preamble Start
Test 4 = SFD Start
Test 3 = Signal Field Start
Test 2 = Length Field Start
Test 1 = Header CRC Start
Test 0 = MPDU Start
TEST_CLK = IQMARK, identifies symbol boundaries on IOUT and QOUT
Bits 7:0
Test Bus Address = 03h
RSSI Monitor
Test 7 = CSE Latched by RSSI Pulse
Test 6 = CSE, Carrier Sense Early (SQI CCA Only)
Test 5:0 = RSSI(5:), bit 5 is MSB, straight binary (000000 = Min, 11111 = Max)
TEST_CLK = RSSI A/D CLK, Sample RSSI(5:0) on last rising edge
Bits 7:0
Test Bus Address = 04h
SQ1 Monitor
Test 7:0 = SQ1 (7:0)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 05h
SQ2 Monitor
Test 7:0 = SQ2 (7:0)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 06h
Correlator Lo Rate
Test 7:0 = Correlator Magnitude Lo Rate Only
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 07h
Freq Test Lo Rate
Test 7:0 = Freq Reg Lo Rate (18:11)
TEST_CLK = SUBSAMPLECLK (Symbol Clock)
Bits 7:0
Test Bus Address = 08h
Phase Test Lo Rate
Test 7:0 = Phase Reg Lo Rate (7:0)
TEST_CLK = SUBSAMPLECLK (Symbol Clock)
Bits 7:0
Test Bus Address = 09h
NCO Test Lo Rate
Test 7:0 = NCO Reg Lo Rate (15:8)
TEST_CLK = SUBSAMPLECLK (Symbol Clock)
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