HFA3860 Datasheet, PDF (6/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

SCLK
SD
HFA3860
FIRST ADDRESS BIT
FIRST DATABIT OUT
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
76 54 3 21
MSB
ADDRESS IN
7654321 0
MSB
DATA OUT
LSB
R/W
CS
NOTES:
1. The HFA3860 always uses the rising edge of SCLK. SD, R/W and CS hold times allow the controller to use either the rising or falling edge.
2. This port operates essentially the same as the HFA 3824 with the exception that the AS signal of the 3824 is not required.
FIGURE 2. CONTROL PORT READ TIMING
SCLK
SD
7654321076543 210
76 54 3 21 0765 4 3 21 0
MSB
ADDRESS IN
MSB
DATA IN
LSB
R/W
CS
FIGURE 3. CONTROL PORT WRITE TIMING
CONFIGURATION
REGISTER
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST
NAME
Part/Version Code
I/O Polarity
TX and RX Control
A/D_CAL_POS Register
A/D_CAL_NEG Register
CCA Antenna Control
Preamble Length
Scramble_Tap (RX and TX)
RX_SQ1_ ACQ (High) Threshold
RX-SQ1_ ACQ (Low) Threshold
RX_SQ2_ ACQ (High) Threshold
RX-SQ2_ ACQ (Low) Threshold
SQ1 CCA Thresh (High)
SQ1 CCA Thresh (Low)
ED or RSSI Thresh
SFD Timer
Signal Field (BPSK - 11 Chip Sequence)
Signal Field (QPSK - 11 Chip Sequence)
TYPE
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER
ADDRESS HEX
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
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