HFA3860 Datasheet, PDF (5/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
Pin Descriptions (Continued)
NAME
PIN
TYPE I/O
DESCRIPTION
TEST_CK
1
O
This is the clock that is used in conjunction with the data that is being output from the test bus (TEST
0-7).
RESET
28
I
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3860 goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up. After RESET is de-activated, RX_PE must be activated for at least 2 MCLKs before RX and
TX functions are restored.
MCLK
30
I
Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to
generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
I_OUT
48
O
TX Spread baseband I digital output data. Data is output at the chip rate.
Q_OUT
47
O
TX Spread baseband Q digital output data. Data is output at the chip rate.
NOTE: Total of 48 pins; ALL pins are used.
External Interfaces
There are three primary digital interface ports for the
HFA3860 that are used for configuration and during normal
operation of the device as shown in Figure 1. These ports
are:
• The Control Port, which is used to configure, write and/or
read the status of the internal HFA3860 registers.
• The TX Port, which is used to accept the data that needs
to be transmitted from the network processor.
• The RX Port, which is used to output the received
demodulated data to the network processor.
In addition to these primary digital interfaces the device
includes a byte wide parallel Test Port which can be
configured to output various internal signals and/or data.
The device can also be set into various power consumption
modes by external control. The HFA3860 contains three
Analog to Digital (A/D) converters. The analog interfaces to
the HFA3860 include, the In phase (I) and quadrature (Q)
data component inputs, and the RF signal strength indicator
input. A reference voltage divider is also required external to
the device.
ANTSEL
HFA3860
ANALOG
INPUTS
A/D
REFERENCE
POWER
DOWN
SIGNALS
TEST
PORT
I (ANALOG)
Q (ANALOG)
TXD
RSSI (ANALOG) TXCLK
TX_RDY
V_REFN
V_REFP
RXD
RXC
TX_PE
RX_PE
MD_RDY
CS
SD
RESET
SCLK
8
R/W
TEST
SDI
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE 1. EXTERNAL INTERFACE
Control Port (4 Wire)
The serial control port is used to serially write and read data
to/from the device. This serial port can operate up to a
11MHz rate or 1/2 the maximum master clock rate of the
device, MCLK (whichever is lower). MCLK must be running
during programming. This port is used to program and to
read all internal registers. The first 8 bits always represent
the address followed immediately by the 8 data bits for that
register. The two LSBs of address are don’t care, but
reserved for future expansion. The serial transfers are
accomplished through the serial data pin (SD). SD is a
bidirectional serial data bus. Chip Select (CS), and
Read/Write (R/W) are also required as handshake signals
for this port. The clock used in conjunction with the address
and data on SD is SCLK. This clock is provided by the
external source and it is an input to the HFA3860. The timing
relationships of these signals are illustrated in Figures 2 and
3. R/W is high when data is to be read, and low when it is to
be written. CS is an asynchronous reset to the state
machine. CS must be active (low) during the entire data
transfer cycle. CS selects the serial control port device only.
The serial control port operates asynchronously from the TX
and RX ports and it can accomplish data transfers
independent of the activity at the other digital or analog
ports.
The HFA3860 has 32 internal registers that can be accessed
through the control port. These registers are listed in the
Configuration and Control Internal Register table. Table 1 lists
the configuration register number, a brief name describing the
register, and the HEX address to access each of the registers.
The type indicates whether the corresponding register is
Read only (R) or Read/Write (R/W). Some registers are two
bytes wide as indicated on the table (high and low bytes).
See Tech Brief #360 on timing issues between the serial
clock (SCLK) and the chip master clock (MCLK).
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