HFA3860 Datasheet, PDF (34/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued)
Supplies address for test pin outputs and Test Bus Monitor Register
Bits 7:0
Test Bus Address = 17h
XOR Fast, Factory Test Only
Test 7:0 + TEST_CLK = 9 bits of registered XOR test data from the low rate logic.
Bits 7:0
Test Bus Address = 18h
Timing Test, tests the receiver timing.
Test 7 = JMPCLK
Test 6 = JMPCNT
Test 5 = SUBSAMPLECLK
Test 4:0 = MASTERTIM(4:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 19h
A/D Cal Accum Lo, tests the lo bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (8:0)
Bits 7:0
Test Bus Address = 1Ah
A/D Cal Accum Hi, tests the hi bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (17:9)
Bits 7:0
Test Bus Address = 1Bh
Freq Accum Lo, tests the frequency accumulator of the low rate section.
Test 7:0+TestCLK = Freq Accum (15:7)
Bits 7:0
Test Bus Address = 1Ch
Slow XOR, Factory Test
Test 7:0 = 8 bits of registered XOR test data from the low rate logic
TEST_CLK = SUBSAMPLECLK
Bits 7:0
Test Bus Address = 1Dh
SQ2 Monitor Hi
Test 7:0 = SQ2 (15:8)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 1Eh to 1Fh
Reserved
Test 7:0 + TestCLK = 0
Bits 7:0
CONFIGURATION REGISTER 29 ADDRESS (74h) TEST BUS MONITOR
Maps test bus pins 7:0 to read only value 7:0 when test bus address is supplied by CR 28
Bits 7
Bit 6
Bit 5
Bit 4
Bit 3
CONFIGURATION REGISTER 30 ADDRESS (78h) TEST REGISTER 1
PN Generator for Fault Test
0 = Normal
1 = Enabled
Change MUX Control in Subsample Path
0 = Normal
1 = Changed
HR Demod XOR to Test Bus Enable
0 = Normal
1 = Enabled
Random Address to Test Bus
0 = Normal
1 = Enabled
Faster Cal
0 = Normal
1 = Enabled
When enabled, the 1kHz clock used to update the A/D cal bits is increased to 22kHz.
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