HFA3860 Datasheet, PDF (35/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

Bit 2
Bit 1
Bit 0
Bits 7:2
Bit 1
Bit 0
HFA3860
CONFIGURATION REGISTER 30 ADDRESS (78h) TEST REGISTER 1 (Continued)
A/D Cal Test Mode
0 = Normal
1 = Enabled
When enabled, the 5 A/D cal bits come from CR3<4:0> to allow direct control.
A/D Test Mode
0 = Normal
1 = Enabled
When enabled, this bit causes all 12 bits of A/D outputs (6 RSSI, 3 I, 3 Q) to be directly output on pins of the HFA3860.
Modem is non-functional.
Loop Back
0 = Normal
1 = Enabled
When enabled, this bit routes the I and Q outputs to the I and Q inputs of the modem. The 3-bit I&Q A/Ds are bypassed.
CONFIGURATION REGISTER 31 ADDRESS (7Ch) TEST REGISTER 2
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Disable Control
0 = ED disabled 19µs after RXPE active
1 = ED runs continuously, updates every ANT Dwell
CCA Type Select
0 = RAWCCA, updates every ANT Dwell
1 = Snapshot (Latched) CCA
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