HFA3860 Datasheet, PDF (39/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

TX_PE
t_D1
I_OUT, Q_OUT
TXRDY
TX_CLK
TXD
HFA3860
t_PEH
t_TCD t_TCD
t_RC
t_TDS
t_TDH
FIGURE 21. TX PORT SIGNAL TIMING
t_TLP
t_ME
t_RI
RX_PE
I_IN, Q_IN
MD_RDY
RX_CLK
RXD
CCA, RSSI
t_RLP
t_RD3
t_REH
t_RCP
t_RD2
t_CCA
t_RCD ^tRCD
t_{RD1 tRDD} t_RDS
NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output on TEST (5:0).
FIGURE 22. RX PORT SIGNAL TIMING
MCLK
t_D2
TEST 0-7, CCA, ANTSEL, TEST_CK
RESET
t_RPW
MCLK
t_CP
NOTE: Delays will occur from rising or falling edige of MCLK if CR2 Bit 7 is set to a 1.
FIGURE 23. MISCELLANEOUS SIGNAL TIMING
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