HFA3860 Datasheet, PDF (14/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
compliance with IEEE 802.11.
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(MPDU). The external controller will check the length field in
determining when it needs to de-assert the RX_PE.
CCITT - CRC 16 Field (16 Bits)- This field includes the 16-
bit CCITT - CRC 16 calculation of the five header fields. This
value is compared with the CCITT - CRC 16 code calculated
at the receiver. The HFA3860 receiver will indicate a CCITT -
CRC 16 error via CR24 bit 2 and will lower MD_RDY if there
is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x¹⁶ + x¹² + x⁵ + 1
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 6
Defines the preamble length in symbols. The 802.11 protocol
requires a setting of 128d = 80h.
CR 15 - Defines the length of time that the demodulator
searches for the SFD before returning to acquisition.
CR 16. The contents of this register define DBPSK modulation.
If CR 20 bits 1 and 0 are set to indicate DBPSK modulation
then the contents of this register are transmitted in the signal
field of the header.
CR 17. The contents of this register define DQPSK modulation.
If CR 20 bits 1 and 0 are set to indicate DQPSK modulation
then the contents of this register are transmitted in the signal
field of the header.
CR 18. The contents of this register define BMBOK modula-
tion. If CR 20 bits 1 and 0 are set to indicate BMBOK modula-
tion then the contents of this register are transmitted in the
signal field of the header.
CR 19. The contents of this register define QMBOK modula-
tion. If CR 20 bits 1 and 0 are set to indicate QMBOK modula-
tion then the contents of this register are transmitted in the
signal field of the header.
CR 20. The last two bits of the register indicate what modula-
tion is to be used for the data portion of the packet.
CR 21. The value to be used in the Service field.
CR 22, 23. Defines the value of the transmit data length field.
This value includes all symbols following the last header field
symbol and is in microseconds required to transmit the data at
the chosen data rate.
The packet consists of the preamble, header and MAC
protocol data unit (MPDU). The data is transmitted exactly as
received from the control processor. Some dummy bits will be
appended to the end of the packet to insure an orderly
shutdown of the transmitter. This prevents spectrum splatter.
At the end of a packet, the external controller is expected to
de-assert the TX_PE line to shut the transmitter down.
PREAMBLE (SYNC) SFD
128 BITS
16 BITS
PREAMBLE
SIGNAL FIELD
8 BITS
SERVICE FIELD LENGTH FIELD CRC16
8 BITS
16 BITS
16 BITS
HEADER
FIGURE 9. 802.11 PREAMBLE/HEADER
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consist of a 7-bit shift register with feedback from specified
taps of the register, as programmed through configuration
register CR 7. Both transmitter and receiver use the same
scrambling algorithm. The scrambler can be disabled by
setting the taps to 0.
Scrambling is done by a polynomial division using a
prescribed polynomial as shown in Figure 10. A shift register
holds the last quotient and the output is the exclusive-or of
the data and the sum of taps in the shift register. The taps
are programmable. The transmit scrambler seed is Hex 6C
and the taps are set with CR 7.
SERIAL DATA
INPUT
Z^-1 Z^-2 Z^-3 Z^-4
Z^-5 Z^-6 Z^-7
XOR
XOR
SERIAL DATA
OUTPUT
FIGURE 10. SCRAMBLING PROCESS
For the 1 Mbps DBPSK data rates and for the header in all
rates, the data coder implements the desired DBPSK coding by
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