HFA3860 Datasheet, PDF (25/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
differential decoding and descrambling. For the 5.5 and 11
MBps modes, the errors occur in symbols of 4 or 8 bits each
and are further extended by the descrambling. Therefore the
error patterns are less well defined.
1.E^-02
1.E^-03
BER 2.0
1.E^-04
THY 1,2
BER 1.0
1.E^-05
1.E^-06
1.E^-07
5 6 7 8 9 10 11 12 13 14
EB/N0
FIGURE 15. BER vs EB/N0 PERFORMANCE FOR PSK MODES
1.E-03
1.E-04
1.E-05
1.E-06
THY 5.5
THY 11
BER 11
BER 5.5
1.00E^-03
1.00E^-04
1.00E^-05
1.00E^-06
BER 1.0
BER 2.0
BER 5.5
BER 11
1.00E^-07
-100 -80 -60 -40 -20 0 20 40 60 80 100
CLOCK OFFSET (PPM)
FIGURE 17. BER vs CLOCK OFFSET
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for
demodulation in the 1 and 2 MBps modes are time invariant
matched filter correlators otherwise known as parallel
correlators. They use two samples per chip and are tapped at
every other shift register stage. Their performance with carrier
frequency offsets is determined by the phase roll rate due to
the offset. For an offset of +50ppm (combined for both TX and
RX) will cause the carrier to phase roll 22.5 degrees over the
length of the correlator. This causes a loss of 0.22dB in
correlation magnitude which translates directly to Eb/N0
performance loss. In the PRISM chip design, the correlator is
not included in the carrier phase locked loop correction, so
this loss occurs for both acquisition and data. In the high rate
modes, the data demodulation is done with a set of correlators
that are included in the carrier tracking loop, so the loss is
less. Figure 18 shows the loss versus carrier offset taken out
to +50ppm (120kHz is 50ppm at 2.4GHz).
1.E-07
5 6 7 8 9 10 11 12 13 14
Eb/N0
FIGURE 16. BER vs EB/N0 PERFORMANCE FOR MBOK MODES
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to ±25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at ±50ppm and the performance is shown in
Figure 17. This figure shows that the baseband processor in
the high rate modes is better than at low rates in tracking
clock offsets. The data for Figure 17 and Figure 18 was
taken with the SNR into the receiver set to achieve 1E^-5 BER
with no offset. Then the offset was varied to determine the
change in performance.
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