HFA3860 Datasheet, PDF (24/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
Data Demodulation and Tracking
Description (BMBOK and QMBOK Modes)
This demodulator handles the M-ary Bi-Orthogonal Keying
(MBOK) modulation used for the two highest data rates. It is
slaved to the low rate processor which it depends on for
initial timing and phase tracking information. The high rate
section coherently processes the signal, so it needs to have
the I and Q Channels properly oriented and phased. The low
rate section acquires the signal, locks up symbol and carrier
tracking loops, and determines the data rate to be used for
the MPDU data.
The demodulator for the MBOK modes takes over when the
preamble and header have been acquired and processed. On
the last bit of the header, the absolute phase of the signal is
captured and used as a phase reference for the high rate
demodulator as shown in Figure 14. The phase and
frequency information from the carrier tracking loop in the low
rate section is passed to the loop of the high rate section and
control of the demodulator is passed to the high rate section.
The signal from the A/D converters is carrier frequency and
phase corrected by a complex multiplier (mixer) that multiplies
the received signal with the output of the Numerically
Controlled Oscillator (NCO) and SIN/COS look up table. This
removes the frequency offset and aligns the I and Q Channels
properly for the correlators. The sample rate is decimated to
11 MSPS for the correlators after the complex multiplier since
the data is now synchronous in time.
The Walsh correlation section consists of a bank of 8 serial
correlators on I and 8 on Q. Each of these correlators is
programmed to correlate for its assigned spread function or
its inverse. The demodulator knows the symbol timing, so
the correlation is integrated over each symbol and sampled
and dumped at the end of the symbol. The sampled
correlation outputs from each bank are compared to each
other in a biggest picker and the chosen one determines 4
bits of the symbol. Three bits come from which of the 8
correlators had the largest output and the fourth is
determined from the sign of that output. In the 5.5 Mbps or
binary mode, only the I Channel is operated. This
demodulates 4 bits per symbol. In the 11 Mbps mode, both I
and Q Channels are used and this detects 8 bits per symbol.
The outputs are corrected for absolute phase and then
serialized for the descrambler.
Chip tracking is performed on the de-rotated signal samples
from the complex multiplier. These are alternately routed into
two streams. The END chip samples are the same as those
used for the correlators. The MID chip samples should lie on
the chip transitions when the tracking is perfect. A chip phase
error is generated if the END sign bits bracketing the MID
samples are different. The sign of the error is determined by
the sign of the END sample after the MID sample.
Tracking is only measured when there is a chip transition.
Note that this tracking is mainly effective since there is a
positive SNR in the chip rate bandwidth.
The symbol clock is generated by selecting one 44MHz
clock pulse out of every 32 pulses of the sample clock. Chip
tracking adjusts the sampling in 1/8th chip increments by
selecting which edge of the 44MHz clock to use and which
pulse. Timing adjustments can be made every 32 symbols
as needed.
Carrier tracking is performed in a four phase Costas loop. The
initial conditions are copied into the loop from the carrier loop
in the low rate section. The END samples from above are
used for the phase detection. The phase error for the 11 Mbps
case is derived from Isign*Q-Qsign*I whereas in binary mode,
it is simply Isign*Q. This forms the error term that is integrated
in the lead/lag filter for the NCO, closing the loop.
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HSP3726 IF limiter and the PRISM recommended IF filters.
Off the shelf test equipment are used for the RF processing.
The curves should be used as a guide to assess
performance in a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 15 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation as well as the
PRISM performance measured for DBPSK and DQPSK. The
theoretical performance for BPSK and QPSK is the same as
shown on the diagram. Figure 16 shows the theoretical and
actual performance of the MBOK modes. The losses in both
figures include RF and IF radio losses; they do not reflect the
HFA3860 losses alone. The HFA3860 baseband processing
losses from theoretical are, by themselves, a small
percentage of the overall loss.
The PRISM demodulator performs with an implementation
loss of less than 3dB from theoretical in a AWGN environment
with low phase noise local oscillators. For the 1 and 2 MBps
modes, the observed errors occurred in groups of 4 and 6
errors. This is because of the error extension properties of
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