HFA3860 Datasheet, PDF (16/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
There are two measures that are used in the CCA assessment.
The receive signal strength (RSSI) which measures the energy
at the antenna and carrier sense early (CSE). Both indicators
are normally used since interference can trigger the signal
strength indication, but it might not trigger the carrier sense.
The carrier sense, however, becomes active only when a
spread signal with the proper PN code has been detected, so it
may not be adequate in itself. The CCA compares these
measures to thresholds at the end of each antenna dwell
following RX_PE going active. The CCA, by design, indicates
busy from the time RX_PE goes high until the CCA
assessment is made. CCA should be sampled 16µs after
raising RX_PE.
The receive signal strength indication (RSSI) measurement
is an analog input to the HFA3860 from the successive IF
stage of the radio. The RSSI A/D converts it within the
baseband processor and it compares it to a programmable
threshold. This threshold is normally set to between -70
and -80dBm. A MAC controlled calibration procedure can
be used to optimize this threshold. This measure is used in
the clear channel assessment logic.
The CSE (Carrier Sense Early) is a signal that goes active
when SQ1 (after an antenna dwell) has been satisfied. It is
called early, since it is indicated before the carrier sense
used for acquisition. It is calculated on the basis of the
integrated energy in the correlator output over a block of 15
symbols. Thus, the CCA is valid after 16µs has transpired
from the time RX_PE was raised.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming
details on these registers can be found under the Control
Registers section of this document).
The CCA output from pin 32 of the device can be defined as
active high or active low through CR 1 (bit 5). The RSSI
threshold is set through CR14. If the actual RSSI value from the
A/D exceeds this threshold then ED becomes active.
The instantaneous RSSI value can be monitored by the
external network processor by reading the test bus in mode 3. It
only measures the signal 16µs after the receiver becomes
active. The programmable threshold on the CSE measurement
is set through CR12 and CR13. More details on SQ1 are
included in the receiver section of this document.
In a typical single antenna system CCA will be monitored to
determine when the channel is clear. Once the channel is
detected busy, CCA should be checked periodically to
determine if the channel becomes clear. CCA is stable to allow
asynchronous sampling or even falling edge detection of CCA.
Once MD_RDY goes active, CCA is then ignored for the
remainder of the message. Failure to monitor CCA until
MD_RDY goes active (or use of a time-out circuit) could result
in a stalled system as it is possible for the channel to be busy
and then become clear without an MD_RDY occurring.
A Dual antenna system has the added complexity that CCA
will potentially toggle between active and inactive as each
antenna is checked. The user must avoid mistaking the
inactive CCA signal as an indication the channel is clear. A
time-out circuit that begins with the first busy channel
indication could be used. Alternatively CCA could be
monitored for a clear channel indication for 2 successive
antenna dwells which would show the channel clear on both
antennas. Time alignment of CCA monitoring with the
receiver’s 16µs antenna dwells would required. Once the
receiver has acquired, CCA should be monitored for loss of
signal until MD_RDY goes active.
CR5 selects the starting antenna used when RXPE is
brought active.
CSE is updated at the end of each antenna dwell. After
acquisition, CSE is updated every 64 symbols. In the event
of signal loss after acquisition, CSE may go inactive.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, BMBOK, or QMBOK symbols. The
demodulator includes a frequency tracking loop that tracks
and removes the carrier frequency offset. In addition it tracks
the symbol timing, and differentially decodes (where
appropriate) and descrambles the data. The data is output
through the RX Port to the external processor.
The PRISM baseband processor, HFA3860 uses differential
demodulation for the initial acquisition portion of the
message processing and then switches to coherent
demodulation for the rest of the acquisition and data
demodulation. The HFA3860 is designed to achieve rapid
settling of the carrier tracking loop during acquisition. Rapid
phase fluctuations are handled with a relatively wide loop
bandwidth. Coherent processing improves the BER
performance margin as opposed to differentially coherent
processing and is necessary for processing the two higher
data rates.
The baseband processor uses time invariant correlation to strip
the PN spreading and phase processing to demodulate the
resulting signals in the header and DBPSK/DQPSK
demodulation modes. These operations are illustrated in Figure
14 which is an overall block diagram of the receiver processor.
In processing the DBPSK header, input samples from the I and
Q A/D converters are correlated to remove the spreading
sequence. The peak position of the correlation pulse is used to
determine the symbol timing. The sample stream is decimated
to the symbol rate and the phase is corrected for frequency
offset prior to PSK demodulation. Phase errors from the
demodulator are fed to the NCO through a lead/lag filter to
maintain phase lock. The variance of the phase error is used to
determine signal quality for acquisition and lock detection. The
4-16