HFA3860 Datasheet, PDF (28/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
CONFIGURATION REGISTER 2 ADDRESS (08h) TX AND RX CONTROL
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bit 7
MCLK control.
0 = 44MHz All signal modes supported.
1 = 22MHz 1 and 2 Mbps, B/QPSK 11 Chip sequence mode only. Reduced power mode.
Bit 6
TX Rotation
0 = Normal
1 = Invert Q Out
Bit 5
RX Rotation
0 = Normal
1 = Invert Q IN
Bit4
A/D Calibration
0 = A/D_CAL Off
1 = A/D_CAL On
Bit 3
A/D Calibration control (only valid if A/D Calibration is on).
0 = A/D Calibration only while in receive tracking mode (A/D Calibration set on signals only).
1 = A/D Calibration while receive RX_PE is active (in this mode, the A/D Calibration will be set primarily on noise).
Bit 2
This bit enables/disables energy detect (ED) for the CCA function.
0 = ED Off
1 = ED On
Bit 1
MD_RDY Start. Sets where MD_RDY will become active.
0 = After SFD detect (normal). This allows the header fields to be enveloped by MD_RDY.
1 = After Header CRC verify and start of MPDU. Header data can be read from Configuration Registers.
Bit 0
TX and RX Clock
0 = Enable Gated clocks (normal). RX clock will come on to clock out header fields, go off during CRC and come back on
for MPDU data. Header rate is 1MHz, data rate is variable. TXCLK comes on after TXRDY active.
1 = Clocks start as soon as modem starts tracking and remain on until either header checks fail or until RX_ PE goes back
low. This is only usable in the 1 and 2 Mbps modes. TXCLK comes on after TX_PE active.
Bits 0 - 7
Bits 0 - 7
Bits 7:3
Bit 2
Bits 1:0
Bits 0 - 7
CONFIGURATION REGISTER 3 ADDRESS (0Ch) A/D CAL POS
This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D
reference. The larger the step the faster the A/D Calibration settles.
CONFIGURATION REGISTER 4 ADDRESS (10h) A/D CAL NEG
This 8-bit control register contains a binary value used for the negative increment for the level adjusting circuit of the A/D
reference. The number is programmed as 256 - the value wanted since it is a negative number.
CONFIGURATION REGISTER 5 ADDRESS (14h) CCA ANTENNA CONTROL
R/W, But Not Used Internally
Reserved. Must be set to a 1.
CCA Antenna mode. Defines the antenna to be used at the start of acquisition for CCA checking and for subsequent
transmission. TX antenna is always the same as used to check CCA. Controls antenna selection via the ANT_SEL pin.
00 = Use last Receive antenna for CCA checking and TX. Acquisition starts on the antenna which had a valid header on last
reception.
01 = Illegal State - Unknown Behavior
10 = Use antenna B for CCA and TX. AntSel = 0
11 = Use antenna A for CCA and TX. AntSel = 1
CONFIGURATION REGISTER 6 ADDRESS (18h) PREAMBLE LENGTH
This register contains the count for the Preamble length counter. Setup while TX_PE is low. For IEEE 802.11 use 80h. For
other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition
performance at the cost of greater link overhead. For dual receive antenna operation, the minimum suggested value is 128d = 80h.
For single receive antenna operation, the minimum suggested value is 80d = 50h. These suggested values include a 2 symbol TX
power amplifier ramp up. If you program 128 you get 130.
4-28