HFA3860 Datasheet, PDF (29/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

Bit 7
Bits 6:0
Bits 0 - 7
Bits 0 - 7
Bits 0 - 7
Bits 0 - 7
Bits 0 - 7
Bits 0 - 7
HFA3860
CONFIGURATION REGISTER 7 ADDRESS (1Ch) SCRAMBLER TAPS
0 = Normal, RX_PE Enables/Disables the internal receive clock. I = Internal receive clock is always enabled.
This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scrambler is
a 7-bit shift register, with 7 configurable taps. A logic 1 is the respective bit position enables that particular tap. The example
below illustrates the register configuration for the polynomial F(x) = 1 + X^-4+X^-7. Each clock is a shift left.
Bits (6:0)
Term
Scrambler Taps
F(x) = 1 + X^-4+X^-7
LSB
6543210
X^-7X^-6X^-5X^−4X^-3X^-2X^-1
1001000
CONFIGURATION REGISTER 8 ADDRESS (20h) SQ1 ACQ THRESHOLD (HIGH)
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurements made during acquisition at each antenna dwell. This threshold comparison is added with the SQ2 threshold
in registers 10 and 11 for acquisition. A lower value on this threshold will increase the probability of detection and the
probability of false alarm.
CONFIGURATION REGISTER 9 ADDRESS (24h) SQ1 ACQ THRESHOLD (LOW)
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition at each antenna dwell.
CONFIGURATION REGISTER 10 ADDRESS (28h) SQ2 ACQ THRESHOLD (HIGH)
This control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition. This
register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made
during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used with the bit
sync threshold in registers 8 and 9 to declare acquisition. A higher value in this threshold will increase the probability of
acquisition and false alarm.
CONFIGURATION REGISTER 11 ADDRESS (2Ch) SQ2 ACQ THRESHOLD (LOW)
This control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition.
CONFIGURATION REGISTER 12 ADDRESS (30h) SQ1 CCA THRESHOLD (HIGH)
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for CCA
estimation. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal
quality measurement made during acquisition on CCA antenna dwell. A lower value on this threshold will increase the
probability of detection and the probability of false alarm. Set the threshold according to instructions in the text.
CONFIGURATION REGISTER 13 ADDRESS (34h) SQ1 CCA THRESHOLD (LOW)
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for CCA. This
register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition on CCA antenna dwell.
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