HFA3860 Datasheet, PDF (33/40 Pages) Intersil Corporation – 11 Mbps Direct Sequence Spread Spectrum Baseband Processor

HFA3860
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued)
Supplies address for test pin outputs and Test Bus Monitor Register
Bits 7:0
Test Bus Address = 0Ah
Bit Sync Accum Lo Rate
Test 7:0 = Bit Sync Accumulator (7:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 0Bh
Test PN Gen., Factory Test Only
Test 7:0 +TEST_CLK = Top 9 bits of PN generator used for fault tests.
Bits 7:0
Test Bus Address = 0Ch
A/D Cal Test Mode
Test 7 = A/D CAL (Full Scale)
Test 6 = ED, Energy Detect Comparator Output
Test 5 = A/D_CAL Disable
Test(4:0) = A/D_Cal(4:0)
TEST_CLK =A/D_Cal CLK
Bits 7:0
Test Bus Address = 0Dh
Correlator I High Rate, tests the MBOK I correlator output.
Test 7:0 = Correlator I Hi Rate (8:1)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 0Eh
Correlator Q High Rate, tests the MBOK Q correlator output.
Test 7:0 = Correlator Q Hi Rate (8:1)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 0Fh
Chip Error Accumulator,
Test 7:0 = Chip Error Accumulator (14:7)
TEST_CLK = 0
Bits 7:0
Test Bus Address = 10h
NCO Test Hi Rate, tests the NCO in the high rate tracking section.
Test 7:0 = NCO Accum (19:12)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 11h
FREQ Test Hi Rate, tests the NCO lag accumulator in the high rate tracking section.
Test 7:0 = Lag Accum (18:11)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 12h
Carrier Phase Error Hi Rate
Test 7:0 = Carrier Phase Error (6,6:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 13h
I_ROT Hi Rate, tests the I Channel phase rotation error signal.
Test 7:0 = I_ROT (5,5,5:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 14h
Q_ROT Hi Rate
Test 7:0 = Q_ROT (5,5,5:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 15h
I_A/D, Q_A/D, tests the I and Q Channel 3-bit A/D Converters.
Test 7:6 = 0
Test 5:3 = I_A/D (2:0)
Test 2:0 = Q_A/D (2:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 16h
XOR Hi Rate, Factory Test Only
Test 7:0 + TEST_CLK = 9 bits of registered XOR test data from the high rate logic.
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