82596DX Datasheet, PDF (69/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
SYSTEM INTERFACE A C TIMING CHARACTERISTICS
The measurements should be done at
 T_C ^e 0 C – 85 C V_CC ^e 5V g10% C ^e 50 pF unless otherwise specified
 A C testing inputs are driven at 2 4V for a logic ‘‘1’’ and 0 45V for a logic ‘‘0’’
 Timing measurements are made at 1 5V for both logic ‘‘1’’ and ‘‘0’’
 Rise and Fall time of inputs and outputs signals are measured between 0 8V and 2 0V respectively unless
otherwise specified
 All timings are relative to CLK2 crossing the 1 5V level
 All A C parameters are valid only after 100 ms from power up
290219 – 18
Figure 46 CLK2 Timings
Two types of timing specifications are presented below
1 Input Timing minimum setup and hold times
2 Output Timings output delays and float times from CLK2 rising edge
Figure 45 defines how the measurements should be done
290219 – 19
290219 – 20
LEGEND
Ts e Input Setup Time
Th e Input Hold Time
Tn e Minimum output delay or Mininum float delay
Tx e Maximum output delay or Maximum float delay
Figure 47 Drive Levels and Measurements Points for A C Specifications
69