82596DX Datasheet, PDF (33/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
Bits 20–22 RUC
Bit 23 RESET
(3 bits) This field contains the command to the Receive Unit Valid values are
0
NOP (does not alter current state of unit)
1
Start reception of frames The beginning of the RFA is contained in the RFA
OFFSET (address) If a frame is being received complete reception before
starting
2
Resume frame reception (only when in suspended state)
3
Suspend frame reception If a frame is being received complete its reception
before suspending
4
Abort receiver operation immediately
5–7 Reserved
Reset chip (logically the same as hardware RESET)
Status Word
15
STAT
82586 Mode
0
0
CUS
0
RUS
0
0
0
0 SCB
15
STAT
0
CUS
32-Bit Segmented and Linear Modes
RUS
0
T
0
0
0 SCB
Indicates the status of the 82596 This word is modified only by the 82596 Defined bits are
Bit 15 CX
The CU finished executing a command with its I (interrupt) bit set
Bit 14 FR
The RU finished receiving a frame
Bit 13 CNA
The Command Unit left the Active state
Bit 12 RNR
The Receive Unit left the Ready state
Bits 8–10 CUS
(3 bits) This field contains the status of the command unit Valid values are
0
Idle
1
Suspended
2
Active
3–7 Not used
Bits 4–7 RUS
This field contains the status of the receive unit Valid values are
0h (0000) Idle
1h (0001) Suspended
2h (0010) No resources This bit indicates both no resources due to lack of RFDs
in the RDL and no resources due to lack of RBDs in the FBL
4h (0100) Ready
Ah (1010) No resources due to no more RBDs (Not in the 82586 mode )
Ch (1100) No more RBDs (not in the 82586 mode)
No other combinations are allowed
Bit 3 T
Bus Throttle timers loaded (not in 82586 mode)
SCB OFFSET ADDRESSES
CBL Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
first Command Block on the CBL In Linear mode it is a 32-bit linear address for the first Command Block on
the CBL It is accessed only if CUC equals Start
33