82596DX Datasheet, PDF (12/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
PORT
3
I PORT When this signal is received the 82596 latches the data on the
data bus into an internal 32-bit register When the CPU is asserting this
signal it can write into the 82596 (via the data bus) This pin must be
activated twice during all CPU Port access commands
RESET
69
I RESET This active high internally synchronized signal causes the
82596 to terminate current activity The signal must be high for at least
five system clock cycles After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal When RESET returns to low the 82596 waits for the
first CA signal and then begins the initialization sequence
LE BE
65
I LITTLE ENDIAN BIG ENDIAN This dual-function pin is used to
select byte ordering When LE BE is high little endian byte ordering is
used when low big endian byte ordering is used for data in frames
(bytes) and for control (SCB RFD CBL etc )
CA
119
I CHANNEL ATTENTION The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks The CA signal is
internally synchronized The signal must be high for at least one
system clock It is latched internally on the high to low edge and then
detected by the 82596
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an SCP address written
to the 82596 using CPU Port access All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB
INT INT
125
O INTERRUPT A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt This signal is an edge triggered interrupt
signal and can be configured to be active high or low
V_CC
18 Pins (DX)
19 Pins (SX)
POWER ^a5V g10%
V_SS
19 Pins
(DX and SX)
GROUND 0V
TxD
54
O TRANSMIT DATA This pin transmits data to the serial link It is high
when not transmitting
TxC
64
I TRANSMIT CLOCK This signal provides the fundamental timing for
the serial subsystem The clock is also used to transmit data
synchronously on the TxD pin For NRZ encoding data is transferred
to the TxD pin on the high to low clock transition For Manchester
encoding the transmitted bit center is aligned with the low to high
transition Transmit clock should always be running for proper device
operation
12