82596DX Datasheet, PDF (28/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
MEMORY ADDRESSING FORMATS
The 82596 accesses memory by 32-bit addresses There are two types of 32-bit addresses linear and seg-
mented The type of address used depends on the 82596 operating mode and the type of memory structure it
is addressing The 82596 has three operating modes
 82586 Mode
 A Linear address is a single 24-bit entity Address pins A₃₁ – A₂₄ are always zero
 A Segmented address uses a 24-bit base and a 16-bit offset
 32-bit Segmented Mode
 A Linear address is a single 32-bit entity
 A Segmented address uses a 32-bit base and a 16-bit offset
NOTE
In the previous two memory addressing modes each command header (CB TBD RFD RBD and SCB)
must wholly reside within one segment If the 82596 encounters a memory structure that does not follow this
restriction the 82596 will fetch the next contiguous location in memory (beyond the segment)
 Linear Mode
 A Linear address is a single 32-bit entity
 There are no Segmented addresses
Linear addresses are primarily used to address transmit and receive data buffers In the 82586 and 32-bit
Segmented modes segmented addresses (base plus offset) are used for all Command Blocks Buffer Descrip-
tors Frame Descriptors and System Control Blocks When using Segmented addresses only the offset
portion of the entity being addressed is specified in the block The base for all offsets is the same that of the
SCB See Table A
LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures
The 82596A1 stepping supports Big Endian byte ordering for word and byte entities Dword entities are not
supported with 82596A1 Big Endian byte ordering This results in slightly different 82596 memory structures
for Big Endian operation These structures are defined in the 32-Bit LAN Components A1 Manual
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