82596DX Datasheet, PDF (11/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
WR
120
O
WRITE READ This dual-function pin is used to distinguish Write and
Read cycles This line is floated after a Reset or when the bus is not
acquired
ADS
124
O
ADDRESS STATUS This tri-state pin is used by the 82596 to indicate
that a valid bus cycle has begun and that A31 – A2 BE3 – BE0 and
W R are being driven It is asserted during t1 bus states This line is
floated after a Reset or when the bus is not acquired
RDY
130
I
READY Active low This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed When
high it causes wait states to be inserted It is ignored at the end of the
first clock of the bus cycle’s data cycle This active-low signal does not
have an internal pull-up resistor This signal must meet the setup and
hold times to operate correctly
LOCK
126
O
LOCK This tri-state pin is used to distinguish locked and unlocked bus
cycles LOCK generates a semaphore handshake to the CPU LOCK
can be active for several memory cycles it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2) This line is floated after a Reset or when the bus is not acquired
LOCK can be disabled via the sysbus byte in software
BS16
129
I
BUS SIZE This signal allows the 82596DX to work with either 16- or
32-bit bytes This signal is static and should be tied high for 32-bit
operation or low for 16-bit operation In Little Endian mode the D0 –
D15 lines are driven when BS16 is inserted in Big Endian mode the
D16–D31 lines are driven
HOLD
123
O
HOLD The HOLD signal is active high the 82596 uses it to request
local bus mastership In normal operation HOLD goes inactive before
HLDA The 82596 can be forced off the bus by deasserting HLDA or if
the bus throttle timers expire
HLDA
118
I
HOLD ACKNOWLEDGE The HLDA signal is active high it indicates
that bus mastership has been given to the 82596 HLDA is internally
synchronized after HOLD is detected low the CPU drives HLDA low
NOTE
Do not connect HLDA to V_CC it will cause a deadlock A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD If HLDA goes inactive before HOLD the 82596 will release
the bus (by deasserting HOLD) within a specified number of system
clocks
BREQ
115
I
BUS REQUEST This signal when configured to an externally
activated mode is used to trigger the bus throttle timers
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