82596DX Datasheet, PDF (64/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
A C CHARACTERISTICS (Continued)
82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T_C ^e 0 C to ^a85 C V_CC ^e 5V g10%
These timings assume the C_L on all outputs is 50 pF unless otherwise specified C_L can be 20 pF to 120 pF
however timings must be derated
All timing requirements are given in nanoseconds
Symbol
T1
T2
T3
T4
T5
T13
T14
T26
T25
T6
T6b
T7
T8
T9
T10
T11
T27
T28
T29
T30
T17
T18
T19
T20
T12
Parameter
Operating Frequency
CLK2 Period
CLK2 High
CLK2 Low
CLK2 Rise Time
CLK2 Fall Time
CA and BREQ Setup Time
CA and BREQ Hold Time
CA and BREQ PORT Pulse Width
INT Valid Delay
BHE BLE BON and A1–A31 Valid Delay
LOCK Valid Delay
BHE BLE LOCK BON and A1– A31 Float Delay
W R and ADS Valid Delay
W R and ADS Float Delay
D0–D15 Write Data Valid Delay
D0–D15 Write Data Float Delay
D0–D15 CPU PORT Access Setup Time
D0–D15 CPU PORT Access Hold Time
PORT Setup Time
PORT Hold Time
RDY Setup Time
RDY Hold Time
D0–D15 READ Setup Time
D0–D15 READ Hold Time
HOLD Valid Delay
16 MHz
Min
Max
12 5 MHz 16 MHz
31
40
9
9
8
8
11
8
4 T1
1
40
3
36
1
33
4
40
1
33
4
35
3
40
4
35
9
6
11
8
19
6
9
6
2
33
Notes
CLK2 2
2 0V
2 0V
0 8V to 3 7V
3 7V to 0 8V
123
123
3
2
2
2
2
2
2
2
2
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