82596DX Datasheet, PDF (10/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
PIN DESCRIPTIONS
Symbol
PQFP
Pin No
Type
CLK2
9
I
D31 – D0
14 – 53
IO
(D15–D0) 14–32
IO
A31 – A2
70 – 108
O
A1
112
O
BE3 –BE0 109–114 O
BHE BLE 113–114 O
BON
109
O
Name and Function
CLOCK The system clock input provides the fundamental timing for
the 82596 It is internally divided by two to generate the 82596 clock
All external timing parameters are specified in reference to the rising
edge of CLK2 For clock levels see D C Characteristics
DATA BUS The 32 Data Bus lines are bidirectional tri-state lines that
provide the general purpose data path between the 82596 and
memory With the 82596DX the bus can be either 16 or 32 bits wide
this is determined by the BS16 signal which is static The 82596
always drives all 32 data lines during Write operations even with a
16-bit bus D0 – D31 are floated after a Reset or when the bus is not
acquired
These lines are inputs during a CPU Port access in this mode the CPU
writes the next address to the 82596 through the Data lines During
PORT commands (Relocatable SCP Self-Test and Dump) the
address must be aligned to a 16 byte boundary This frees the D₃ – D₀
lines so they can be used to distinguish the commands The following
is a summary of the decoding data
D0 D1 D2 D3 D4 – D31
Function
0000
0000 Reset
0 1 0 0 ADDR Relocatable SCP
1 0 0 0 ADDR Self-Test
1 1 0 0 ADDR Dump Command
These 16 Data Bus lines are bidirectional tri-state lines that provide
the entire data path for the 82596SX In the 82596SX D16 – D31 are
not connected (NC)
ADDRESS LINES These 30 tri-stated Address lines output the
address bits required for memory operation These lines are floated
after a Reset or when the bus is not acquired
The 82596SX requires this additional address line to output the
address bits required for memory operation
BYTE ENABLE (82596DX only ) These tri-stated signals are used to
indicate which bytes are involved with the current memory access The
number of Byte Enable signals asserted indicates the physical size of
the data being transferred (1 2 3 or 4 bytes)
 BE0 indicates D0–D7
 BE1 indicates D8–D15
 BE2 indicates D16–D23
 BE3 indicates D24–D31
These lines are floated after a Reset or when the bus is not acquired
(82596SX only ) These signals are the Byte High Enable and Byte Low
Enable signals for the 82596SX
BUS ON (82596SX only ) This signal is driven high when the 82596 is
holding the bus This signal is tri-stated when the bus is relinquished
BON has the same timing as the Byte Enables
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