82596DX Datasheet, PDF (38/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
31
ODD WORD
16 15
EVEN WORD
0
EL S I 0 0 0 0 0 0 0 0 0 0 0 1 0 C B OK A 0 0 0 0 0 0 0 0 0 0 0 0 0
A31
LINK ADDRESS
A0 4
Byte 3
Byte 2
Byte 1
Byte 0
8
Byte 7
Byte 6
Byte 5
Byte 4
12
Byte 11
Byte 10
Byte 9
Byte 8
16
XXXXXXXXXXXXXXXX
Byte 13
Byte 12
20
LINK ADDRESS
EL B C I S
A
Bits 19–28
CMD (bits 16–18)
Figure 25 CONFIGURE Linear Mode
As per standard Command Block (see the NOP command for details)
Indicates that the command was abnormally terminated due to a CU Abort control com-
mand If 1 then the command was aborted and if necessary it should be repeated If this
bit is 0 the command was not aborted
Reserved (zero in the 32-Bit Segmented and Linear Modes)
The CONFIGURE command Value 2h
The interpretation of the fields follows
7
6
P
X
BYTE 0
BYTE CNT (Bits 0–3)
PREFETCHED (Bit 7)
5
4
3
2
1
0
X
X
BYTE COUNT
Byte Count Number of bytes including this one that hold pa-
rameters to be configured
Enable the 82596 to write the prefetched bit in all prefetch
RBDs
NOTE
The P bit is valid only in the new memory structure modes In 82586 mode this bit is disabled
(i e no prefetched mark)
7
MONITOR
BYTE 1
FIFO Limit (Bits 0–3)
MONITOR (Bits 6–7)
DEFAULT C8h
X
X
0
FIFO LIMIT
FIFO limit
Receive monitor options If the Byte Count of the configure
command is less than 12 bytes then these Monitor bits are
ignored
7
SAV BF
1
BYTE 2
RESUME RD (Bit 1)
SAV BF (Bit 7)
DEFAULT 40h
0
0
0
0
0
RESUME RD
0
0 The 82596 does not reread the next CB on the list when a CU RESUME
Control Command is issued
1 The 82596 will reread the next CB on the list when a CU RESUME
Control Command is issued This is available only on the 82596B step-
ping
0 Received bad frames are not saved in the memory
1 Received bad frames are saved in the memory
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