82596DX Datasheet, PDF (63/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
A C CHARACTERISTICS (Continued)
82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T_C ^e 0 C to ^a85 C V_CC ^e 5V g10%
These timings assume the C_L on all outputs is 50 pF unless otherwise specified C_L can be 20 pF to 120 pF
however timings must be derated
All timing requirements are given in nanoseconds
Symbol
Parameter
20 MHz
Min
Max
Notes
Operating Frequency
12 5 MHz
20 MHz
CLK2 2
T1
CLK2 Period
25
40
T2
CLK2 High
8
at 2 0V
T3
CLK2 Low
8
at 2 0V
T4
CLK2 Rise Time
8
0 8V to 3 7V
T5
CLK2 Fall Time
8
3 7V to 0 8V
T13
CA and BREQ Setup Time
10
123
T14
BREQ Hold Time
7
123
T14a
CA Hold Time
8
123
T26
CA and BREQ PORT Pulse Width
4 T1
3
T25
INT Valid Delay
1
35
T6
BHE BLE LOCK BON and A1 – A31
Valid Delay
3
30
T7
BHE BLE LOCK BON and A1 – A31
Float Delay
4
30
T8
W R and ADS Valid Delay
3
26
T9
W R and ADS Float Delay
4
30
T10
D0–D15 Write Data Valid Delay
3
38
T11
D0–D15 Write Data Float Delay
4
27
T27
D0–D15 CPU PORT Access Setup Time
9
2
T28
D0–D15 CPU PORT Access Hold Time
6
2
T29
PORT Setup Time
10
2
T30
PORT Hold Time
7
2
T17
RDY Setup Time
12
2
T18
RDY Hold Time
4
2
T19
D0–D15 READ Setup Time
9
2
T20
D0–D15 READ Hold Time
5
2
T12
HOLD Valid Delay
3
28
T21
HLDA Setup Time
15
12
T22a
HLDA Hold Time
7
12
T23
RESET Setup Time
12
12
T24
RESET Hold Time
4
12
NOTE
Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact
your local Intel representative
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