82596DX Datasheet, PDF (27/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
timers are essentially disabled the T-ON value is infinite the T-OFF value is zero After the SCP is read the
82596 reads the ISCP and saves the SCB address In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks) In Linear mode the base address is also an absolute address The 82596 clears BUSY sets CX and
CNR to equal 1 in the SCB clears the SCB command word sends an interrupt to the CPU and awaits another
Channel Attention signal RESET configures the 82596 to its default state before CA is asserted
CONTROLLING THE 82596DX SX
The host CPU controls the 82596 with the commands data structures and methods described in this section
The CPU and the 82596 communicate through shared memory structures The 82596 contains two indepen-
dent units the Command Unit and the Receive Unit The Command Unit executes commands from the CPU
and the Receive Unit handles frame reception These two units are controlled and monitored by the CPU
through a shared memory structure called the System Control Block (SCB) The CPU and the 82596 use the
CA and INT signals to communicate with the SCB
82596 CPU ACCESS INTERFACE (PORT)
The 82596 has a CPU access interface that allows the host CPU to do four things
 Write an alternative System Configuration Pointer address
 Write an alternative Dump area pointer and perform Dump
 Execute a software reset
 Execute a self-test
The following events initiate the CPU access state
 Presence of an address on the D₃₁ – D₄ data bus pins
 The D₃ – D₀ pins are used to select one of the four functions
 The PORT input pin is asserted as in a regular write cycle
NOTE
The SCP Dump and Self-Test addresses must be 16-byte aligned
The 82596 requires two 16-bit write cycles for a port command The first write holds the internal machines and
reads the first 16 bits the second activates the PORT command and reads the second 16 bits
The PORT Reset is useful when only the 82596 needs to be reset The CPU must wait for 10-system and 5-se-
rial clocks before issuing another CA to the 82596 this new CA begins a new initialization process
The Dump function is useful for troubleshooting No Response problems If the chip is in a No Response state
the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without
disturbing the rest of the system
The Self-Test function can be used for board testing the 82596 will execute a self-test and write the results to
memory
Table 2 PORT Function Selection
Function
Reset
D₃₁
Addresses and Results
A31
Don’t Care
D₄
D₀
D₃
D₂
D₁
D₀
A4
0
0
0
0
Self-Test
A31
Self-Test Results Address
A4
0
0
0
1
SCP
A31
Alternative SCP Address
A4
0
0
1
0
Dump
A31
Dump Area Pointer
A4
0
0
1
1
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