82596DX Datasheet, PDF (65/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
A C CHARACTERISTICS (Continued)
82596SX C-STEP INPUT OUTPUT SYSTEM TIMINGS T_C ^e 0 C to ^a85 C V_CC ^e 5V g10% (Continued)
These timings assume the C_L on all outputs is 50 pF unless otherwise specified C_L can be 20 pF to 120 pF
however timings must be derated
All timing requirements are given in nanoseconds
Symbol
Parameter
16 MHz
Min
Max
Notes
T21
HLDA Setup Time
15
12
T22a
HLDA Hold Time
7
12
T23
RESET Setup Time
13
12
T24
RESET Hold Time
4
12
NOTES
Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact
your local Intel representative
1 RESET HLDA and CA are internally synchronized This timing is to guarantee recognition at next clock for RESET
HLDA and CA
2 All set-up hold and delay timings are at the maximum frequency specification Fmax and must be derated according to
the following equation for operation at lower frequencies
Tderated e (Fmax Fopr) c T
where
Tderated e Specifies the value to derate the specification
Fmax e Maximum operating frequency
Fopr e Actual operating frequency
T e Specification at maximum frequency
This calculation only provides a rough estimate for derating the frequency For more detailed information contact your Intel
sales office for the data sheet supplement
3 CA is internally synchronized if the setup and hold times are met then CA needs to be only 2 T1 BREQ and PORT are
not internally synchronized BREQ must meet setup and hold times and need only be 2 T1 wide
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