82596DX Datasheet, PDF (67/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

TRANSMIT RECEIVE CLOCK PARAMETERS (Continued)
Symbol
Parameter
RECEIVED DATA PARAMETERS (Continued)
T60
RxD Rise Time
T61
RxD Fall Time
CRS AND CDT PARAMETERS
T62
CDT Low to TxC HIGH
External Collision Detect Setup Time
T63
TxC High to CDT Inactive CDT Hold Time
T64
CDT Low to Jam Start
T65
CRS Low to TxC High
Carrier Sense Setup Time
T66
TxC High to CRS Inactive CRS Hold Time
T67
CRS High to Jamming Start
(Internal Collision Detect)
T68
Jamming Period
T69
CRS High to RxC High
CRS Inactive Setup Time
T70
RxC High to CRS High
CRS Inactive Hold Time
INTERFRAME SPACING PARAMETERS
T71
Interframe Delay
EXTERNAL LOOPBACK-PIN PARAMETERS
T72
TxC Low to LPBK Low
T73
TxC Low to LPBK High
NOTES
1 Special MOS levels V_CIL e 0 9V and V_CIH e 3 0V
2 Manchester only
3 Manchester Needs 50% duty cycle
4 1 TTL load a 50 pF
5 1 TTL load a 100 pF
6 NRZ only
7 Abnormal end of transmission CTS expires before RTS
8 Normal end to transmission
9 Programmable value
T71 e N_IFS  T36
where N_IFS e the IFS configuration value
(if N_IFS is less than 12 then N_IFS is forced to 12)
10 Programmable value
T64 e (N_CDF  T36) a x  T36
(If the collision occurs after the preamble)
where
N_CDF e the collision detect filter configuration value and
x e 12 13 14 or 15
11 T68 e 32  T36
12 Programmable value
T67 e (N_CSF  T36) a x  T36
where N_CSF e the Carrier Sense Filter configuration value and
x e 12 13 14 or 15
13 To guarantee recognition on the next clock
82596DX SX
20 MHz
Min
Max
10
10
20
10
20
10
30
10
Notes
10
12
11
9
T36
4
T36
4
67