82596DX Datasheet, PDF (13/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
PIN DESCRIPTIONS (Continued)
Symbol
PQFP
Pin No
Type
Name and Function
LPBK
58
O
LOOPBACK This TTL-level control signal enables the loopback
mode In this mode serial data on the TxD input is routed through the
82C501 internal circuits and back to the RxD output without driving the
transceiver cable To enable this signal both internal and external
loopback need to be set with the Configure command
RxD
60
I
RECEIVE DATA This pin receives NRZ serial data only It must be
high when not receiving
RxC
59
I
RECEIVE CLOCK This signal provides timing information to the
internal shifting logic For NRZ data the state of the RxD pin is
sampled on the high to low transition of the clock
RTS
57
O
REQUEST TO SEND When this signal is low the 82596 informs the
external interface that it has data to transmit It is forced high after a
Reset or when transmission is stopped
CTS
62
I
CLEAR TO SEND An active-low signal that enables the 82596 to
send data It is normally used as an interface handshake to RTS
Asserting CTS high stops transmission CTS is internally synchronized
If CTS goes inactive meeting the setup time to the TxC negative edge
the transmission will stop and RTS will go inactive within at most two
TxC cycles
CRS
63
I
CARRIER SENSE This signal is active low it is used to notify the
82596 that traffic is on the serial link It is only used if the 82596 is
configured for external Carrier Sense In this configuration external
circuitry is required for detecting traffic on the serial link CRS is
internally synchronized To be accepted the signal must remain active
for at least two serial clock cycles (for CRSF^e0)
CDT
61
I
COLLISION DETECT This active-low signal informs the 82596 that a
collision has occurred It is only used if the 82596 is configured for
external Collision Detect External circuitry is required for collision
detection CDT is internally synchronized To be accepted the signal
must remain active for at least two serial clock cycles (for CDTF^e0)
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