82596DX Datasheet, PDF (46/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the
memory model being used
NOTES
1 The Destination Address and the Length Field are sequential of the Length Field immediately follows the
most significant byte of the Destination Address
2 In case the 82596 is configured with No Source Address insertion bit equal to 0 the 82596 inserts its
configured Source Address in the transmitted frame
 In the 82586 mode or when the Simplified memory model is used the Destination and Length fields of the
transmitted frame are taken from the Transmit Command Block
 If the FLEXIBLE memory model is used the Destination and Length fields of the transmitted frame can be
found either in the TCB or TBD depending on the TCB COUNT
3 If the 82596 is configured with the Address Length Field Location equal to 1 the 82596 does not insert its
configured Source Address in the transmitted frame The first (2 ^c Address Length) ^a 2 bytes of the
transmitted frame are interpreted as Destination Address Source Address and Length fields respectively
The location of the first transmitted byte depends on the operational mode of the 82596
 In the 82586 mode it is always the first byte of the first Tx Buffer
 In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT
In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT
field
In the Flexible mode if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT
field If TCB COUNT equals 0 then it is first byte of the first Tx Buffer
 Transmit frames shorter than six bytes are invalid The transmission will be aborted (only in 82586 mode)
because of a DMA Underrun
4 Frames which are aborted during transmission are jammed Such an interruption of transmission can be
caused by any reason indicated by any of the status bits 8 9 10 and 12
JAMMING RULES
1 Jamming will not start before completion of preamble transmission
2 Collisions detected during transmission of the last 11 bits will not result in jamming
The format of a Transmit Buffer Descriptor is
82586 Mode
31
ODD WORD
16 15
13
EVEN WORD
0
NEXT TBD OFFSET
EOF X
SIZE (ACT COUNT)
0
XXXXXXXX
TRANSMIT BUFFER ADDRESS
4
32-Bit Segmented Mode
31
ODD WORD
16 15
13
EVEN WORD
0
NEXT TBD OFFSET
EOF 0
SIZE (ACT COUNT)
0
TRANSMIT BUFFER ADDRESS
4
Linear Mode
31
ODD WORD
16 15
13
EVEN WORD
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOF 0
SIZE (ACT COUNT)
0
NEXT TBD ADDRESS
4
TRANSMIT BUFFER ADDRESS
8
Figure 31
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