82596DX Datasheet, PDF (14/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
82596 AND HOST CPU INTERACTION
The 82596DX SX and the host CPU communicate
through shared memory Because of its on-chip
DMA capability the 82596 can make data block
transfers (buffers and frames) independently of the
CPU this greatly reduces the CPU byte transfer
overhead
NOTE
The 82596DX and 82596SX differ in their address
pin definitions and their data bus sizes Information
in this data sheet applies to both versions unless
otherwise stated
The 82596 is a multitasking coprocessor that com-
prises two independent logical units the Command
Unit (CU) and the Receive Unit (RU) The CU exe-
cutes commands from shared memory The RU han-
dles all activities related to frame reception The in-
dependence of the CU and RU enables the 82596 to
engage in both activities simultaneously the CU
can fetch and execute commands from memory
while the RU is storing received frames in memory
The CPU is only involved with this process after the
CU has executed a sequence of commands or the
RU has finished storing a sequence of frames
The CPU and the 82596 use the hardware signals
Interrupt (INT) and Channel Attention (CA) to initiate
communication with the System Control Block
(SCB) see Figure 4 The 82596 uses INT to alert the
CPU of a change in the contents of the SCB the
CPU uses CA to alert the 82596
The 82596 has a CPU Port Access state that allows
the CPU to execute certain functions without ac-
cessing memory The 82596 PORT pin and data bus
pins are used to enable this feature The CPU can
directly activate four operations when the 82596 is in
this state
 Write an alternative System Configuration Pointer
(SCP) This can be used when the 82596 cannot
use the default SCP address space
 Write a different Dump Command Pointer and ex-
ecute Dump This can be used for troubleshoot-
ing No Response problems
 The CPU can reset the 82596 via software with-
out disturbing the rest of the system
 A self-test can be used for board testing the
82596 will execute a self-test and write the re-
sults to memory
82596 BUS INTERFACE
The 82596DX SX has bus interface timings and pin
definitions that are compatible with Intel’s 32-bit i386
DX and i386 SX microprocessors This eliminates
the need for additional bus interface logic Operating
at 33 MHz the 82596’s bus bandwidth can be as
high as 66 MB s Since Ethernet only requires
1 25 MB s this leaves a considerable amount of
bandwidth for the CPU The 82596 also has a bus
throttle to regulate its use of the bus Two timers can
be programmed through the SCB one controls the
maximum time the 82596 can remain on the bus the
other controls the time the 82596 must stay off the
bus (see Figure 5) The bus throttle can be pro-
grammed to trigger internally with HLDA or external-
ly with BREQ These timers can restrict the 82596
HOLD activation time and improve bus utilization
82596 MEMORY ADDRESSING
The 82596 has a 32-bit memory address range
which allows addressing up to four gigabytes of
memory The 82596 has three memory addressing
modes (see Table 1)
 82586 Mode The 82596 has a 24-bit memory
address range The System Control Block Com-
mand List Receive Descriptor List and Buffer
Descriptors must reside in one 64-kB memory
segment Transmit and Receive buffers can re-
side in a 24-bit address space
 32-Bit Segmented Mode The 82596 has a 32-
bit memory address range The System Control
Block Command List Receive Descriptor List
and Buffer Descriptors must reside in one 64-kB
memory segment Transmit and Receive buffers
can reside in a 32-bit address space
 Linear Mode The 82596 has a 32-bit memory
address range Any memory structure can reside
anywhere within the 32-bit memory address
range
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