82596DX Datasheet, PDF (2/77 Pages) Intel Corporation – HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

82596DX SX
82596DX and 82596SX High-Performance
32-Bit Local Area Network Coprocessor
CONTENTS
PAGE
INTRODUCTION
3
PIN DESCRIPTIONS
10
82596 AND HOST CPU
INTERACTION
14
82596 BUS INTERFACE
14
82596 MEMORY ADDRESSING
14
82596 SYSTEM MEMORY
STRUCTURE
16
TRANSMIT AND RECEIVE MEMORY
STRUCTURES
17
TRANSMITTING FRAMES
20
RECEIVING FRAMES
21
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS
21
NETWORK PLANNING AND
MAINTENANCE
23
STATION DIAGNOSTICS AND SELF-
TEST
24
82586 SOFTWARE COMPATIBILITY
24
INITIALIZING THE 82596
24
SYSTEM CONFIGURATION POINTER
(SCP)
24
Writing the Sysbus
25
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP)
26
INITIALIZATION PROCESS
26
CONTROLLING THE 82596DX SX
27
82596 CPU ACCESS INTERFACE
(PORT )
27
MEMORY ADDRESSING FORMATS
28
LITTLE ENDIAN AND BIG ENDIAN
BYTE ORDERING
28
COMMAND UNIT (CU)
29
RECEIVE UNIT (RU)
30
SYSTEM CONTROL BLOCK (SCB)
30
SCB OFFSET ADDRESSES
33
CONTENTS
CBL Offset (Address)
RFA Offset (Address)
SCB STATISTICAL COUNTERS
Statistical Counter Operation
ACTION COMMANDS AND
OPERATING MODES
NOP
Individual Address Setup
Configure
Multicast-Setup
Transmit
Jamming Rules
TDR
Dump
Diagnose
RECEIVE FRAME DESCRIPTOR
Simplified Memory Structure
Flexible Memory Structure
Receive Buffer Descriptor (RBD)
PGA PACKAGE THERMAL
SPECIFICATION
ELECTRICAL AND TIMING
CHARACTERISTICS
Absolute Maximum Ratings
DC Characteristics
AC Characteristics
82596DX Input Output System
Timings
82596SX Input Output System
Timings
Transmit Receive Clock
Parameters
82596DX SX BUS OPERATION
System Interface A C Timing
Characteristics
Input Waveforms
Serial A C Timing Characteristics
OUTLINE DIAGRAMS
REVISION SUMMARY
2
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