HYB25L128160AC Datasheet, PDF (9/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
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The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. 9_DD must be applied before or at the same time as 9_DDQ to the
specified voltage when the input signals are held in the “NOP” or “DESELECT” state. The power on
voltage must not exceed 9_DD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must
be started at the same time. After power on, an initial pause of 200 µs is required followed by a
precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause
period. Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode Register. Failure to follow these steps may lead
to unpredictable start-up modes.
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The Mode Register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst write) and a special Burst Read and Single Write mode. The
mode set operation must be done before any activate command after the initial power up. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table. BA0 and BA1 have to be set to
“0” to enter the Mode Register.
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The Extended Mode Register controls functions beyond those controlled by the Mode Register.
These additional functions are unique to Mobile RAMs and includes a Refresh Period field (TCR) for
temperature compensated self-refresh and a Partial-Array Self Refresh field (PASR). The PASR
field is used to specify whether only one quarter (bank 0), one half (banks 0 + 1) or all banks of the
SDRAM array are enabled. Disabled banks will not be refreshed in Self-Refresh mode and written
data will get lost. When only bank 0 is selected, it is possible to partially select only half or one
quarter of bank 0. The TCR field has four entries to set Refresh Period during self-refresh
depending on the case temperature of the Mobile RAM devices.
The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 0
and BA1 = 1) and retains the stored information until it is programmed again or the device loses
power. The Extended mode Register must be loaded when all banks are idle, and the controller
must wait the specified time before initiating any subsequent operation. Violating either these
requirements result in unspecified operation. Unused bit A5 to A11 have to be programmed to “0”.
INFINEON Technologies
9
2003-02