HYB25L128160AC Datasheet, PDF (19/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
I‚‡r†
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests are referenced to the 0.9 V crossover point for VDDQ = 1.8 V components. The
transition time is
AC output load
measured between
circuit (details will
9_IH
be
9 and _IL.
defined
All AC measurements
later). Specified W_AC
assume
W and _OH
W_T = 1 ns with
parameters
the
are
measured with a 30 pF only, without any resistive termination and with a input signal of 1V / ns
edge rate.
I/O
30 pF
Measurement conditions for
t_AC and t_OH
3.
4.
If
If
clock rising
W_T is longer
time
than
is longer than 1
1 ns, a time (W_T -
ns, a
1) ns
time
has
(W_T/2 - 0.5) ns has to be added
to be added to this parameter.
to
this
parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
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6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
7. The write recovery time of twr = 14 ns cycles allows the use of one clock cycle for the write
recovery time when the memory operation frequency is equal or less than 72MHz. For all
memory operation frequencies higher than 72MHz two clock cycles for twr are mandatory.
INFINEON recommends to use two clock cylces for the write recovery time in all applications.
INFINEON Technologies
19
2003-02