HYB25L128160AC Datasheet, PDF (8/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax)
0*) 0*)
Operation Mode ^{CAS Latency BT Burst Length Mode Register (Mx)}
Operation Mode
BA1 BA0 M11 M10 M9 M8 M7 Mode
0
0
0
0
0
0
0
Burst Read/
Burst Write
0
0
0
0
1
0
0
Burst Read/
Single Write
Burst Type
M3
Type
0 Sequential
1 Interleave
CAS Latency
M6 M5 M4
000
001
010
011
100
101
110
111
Latency
Reserved
1
2
3
Reserved
Reserved
Burst Length
Length
M2 M1 M0
Sequential Interleave
000
1
1
001
2
2
010
4
4
011
8
8
100
Reserved
101
Reserved
110
1 1 1 full page
*) BA0 and BA1 must be 0, 0 to select the Mode Register (Vs. the Extended Mode
Register)
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INFINEON Technologies
8
2003-02