HYB25L128160AC Datasheet, PDF (6/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
Pin
LDQM
UDQM,
V_DD
V_SS
V_DDQ
V_SSQ
Type Signal Polarity Function
Input Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQMx
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
LDQM and UDQM controls the lower and upper bytes in
x16 SDRAM.
Supply –
–
Power and ground for the input buffers and the core logic.
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
INFINEON Technologies
6
2003-02