HYB25L128160AC Datasheet, PDF (12/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock edge. The mode restores word line after the refresh and no external precharge
command is necessary. A minimum W_RC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array self-
refresh has been set or not.
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The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh
command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external
control signals including the clock are disabled. Returning CKE to high enables the clock and
initiates the refresh exit operation. After the exit command, at least one W_RC delay is required prior to
any access command. Low Power SDRAMs have the possibility to program the refresh period of the
on-chip timer with the use of an appropriate extended MRS command, depending on the maximum
operation case temperature in the application. In partial array self-refresh mode only the selected
banks will be refreshed. Data written to the non activated banks will get lost after a period defined
by tref.
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DQMx has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock edge, data outputs are disabled and become high impedance after two clock periods
(DQM Data Disable Latency
activated, the write operation
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During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal
clock and extends data read and write operations. One clock delay is required for mode entry and
exit (Clock Suspend Latency t_CSL).
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In order to reduce standby power consumption, a power down mode is available. All banks must be
precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode
is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The
Power Down mode does not perform any refresh operations, therefore the device can’t remain in
Power Down mode longer than the Refresh period W( _REF) of the device. Exit from this mode is
performed by taking CKE “high”. One clock delay is required for power down mode entry and exit.
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The Deep Power Down Mode is an unique function on Mobile RAMs with very low standby currents.
All internal voltage generators inside the Mobile RAMs are stopped and all memory data is lost in
this mode. To enter the Deep Power Down mode all banks must be precharged.
INFINEON Technologies
12
2003-02