HYB25L128160AC Datasheet, PDF (26/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
%ÃX…v‡rÃhqÃSrhqÃD‡r……ˆƒ‡
% ÃX…v‡rÃD‡r……ˆƒ‡rqÃi’ÃhÃX…v‡r
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Write B NOP NOP NOP NOP NOP NOP
1 Clk Interval
DQ’s
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
%!ÃX…v‡rÃD‡r……ˆƒ‡rqÃi’ ÃhÃSrhq
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Read B NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DIN A0 don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0 don’t care don’t care
Input data for the Write is ignored.
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
SPT03719
INFINEON Technologies
26
2003-02