HYB25L128160AC Datasheet, PDF (50/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

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HYB/E 25L128160AC
128-MBit Mobile-RAM
12/18/00
01/15/01
01/22/01
02/12/01
02/19/01
03/07/01
04/02/01
07/02/01
08/23/01
09/18/01
11/14/01
25/03/02
28/02/03
First Revision (Target Datasheet)
Various changes after JEDEC Low Power Task Force meeting in
San Jose, Jan 9-10. 01:
Introduction of a Extended Mode Register for temperature-compensated and par-
tial array Self-Refresh
New Deep Power Down Mode
New 54 BGA package with 9 x 6 ball locations and 3 depop rows.
Truth table for Deep Power Down Mode changed according to latest JEDEC pro-
posal some typos corrected
Pin J8 is “A2”
Extended Mode Register “half array BA1=0”
Extended Mode Register, some clarifications
Datasheet changed to “preliminary”
Outline dimensions for BGA packages added
Electrical pinout for x8 added
Full Page Mode added, thruth table clarified
Pin Configuration for x8 devices corrected : LDQM wird NC und UDQM wird DQM
Deep Power Down Exit waveform changed according to JEDEC ballot
Page 10: Change of power-on description to : ”9_DD must be applied before or at the
same time as 9_DDQ to the specified voltage when the input signals are held in the
“NOP” or “DESELECT” state”
Adjusted currents
Introduced CAS Latency 1
Solder Ball Diameter changed
Adjusted currents
Introduced max. package height
Jedec conforming package drawings included
tRCD and tRP for -7.5 changed
Minimum time of deep power down mode added
t_AC for CAS Latency=1 specified
ICC3N (CKE high) changed from 32ma to 35mA for -7.5
and from 28mA to 31mA for -8.0
p.15: values for ICC1 and ICC5 changed
INFINEON Technologies
50
2003-02