HYB25L128160AC Datasheet, PDF (4/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

Functional Block Diagrams
HYB/E 25L128160AC
128-MBit Mobile-RAM
Column Address
Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A11,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
4096 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 1
4096 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 2
4096 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 3
4096 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
Block Diagram: 8Mb x16 SDRAM (12 / 9 / 2 addressing)
SPB04124
INFINEON Technologies
4
2003-02