HYB25L128160AC Datasheet, PDF (7/50 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES

HYB/E 25L128160AC
128-MBit Mobile-RAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQMx at
the positive edge of the clock. The following list shows the truth table for the operation commands.
2SHUDWLRQ
Bank Active
Bank Precharge
Precharge All
Write
Write with Autoprecharge
Read
Read with Autoprecharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Power Down Entry
(Precharge or active
standby)
Device
State
Idle³
Any
Any
Active³
Active³
Active³
Active³
Idle
Any
Active
Any
Idle
Idle
Idle
(Self
Refr.)
Idle
Active⁴
CKE CKE DQM BA0 AP= Addr CS RAS CAS WE
n-1 n
BA1 A10
H
X
X
V
V
V
L
L
H
H
H
X
X
V
L
X
L
L
H
L
H
X
X
X
H
X
L
L
H
L
H
X
X
V
L
V
L
H
L
L
H
X
X
V
H
V
L
H
L
L
H
X
X
V
L
V
L
H
L
H
H
X
X
V
H
V
L
H
L
H
H
X
X
V
V
V
L
L
L
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
L
H
X
X
X
X
X
H
X
X
X
H
H
X
X
X
X
L
L
L
H
H
L
X
X
X
X
L
L
L
H
H
X
X
X
L
H
X
X
X
X
L
H
H
X
H
X
X
X
H
L
X
X
X
X
L
H
H
H
Power Down Exit
Any
H
X
X
X
(Power
Down)
L
H
X
X
X
X
L
H
H
L
Data Write/Output Enable Active
H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable Active
H
X
H
X
X
X
X
X
X
X
Deep Power Down Entry Idle
H
L
X
X
X
X
L
H
H
L
Deep Power Down Exit
Deep⁵
Power
Down
L
H
X
X
X
X
X
X
X
X
Notes:
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not entry in the burst cycle. Address Input for Mode Set (Mode Register Operation)
5. After Deep Power Down mode exit a full new initialisation of the memory device is mandatory.
INFINEON Technologies
7
2003-02