TC11IB Datasheet, PDF (66/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
Clock Generation Unit
The Clock Generation Unit in the TC11IB, shown in Figure 17, consists of an oscillator
circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it losses the lock on the external clock. PLL can provide the 96MHz and 48MHz
clocks.
In general, the Clock Generation Unit (CGU) is controlled through the System Control
Unit (SCU) module of the TC11IB.
XTAL1
Clock Generation Unit
CGU
O scillator ^fOSC
>1
C ircuit
XTAL2
Phase
D e te ct.
VCO
N
D ivider
PLL
Lock
D e te cto r
1
f_VCO ^{M U X}
0
K:1
D ivider
1
MUX
0
System _
CLK
f_SYS =
96 MHz
K:2
D ivider
1
MUX
0
System _
CLK
f_SYS =
48 MHz
O S C _ F A IL
PLL Deep NDIV VCO_ VCO_ KDIV PLL_ PLL_ PLL_
Locked Sleep [5:0] SEL BYPASS [3:0] 2EN 2SEL BYPASS
[1:0]
System Control Unit
SCU
R egister PLL_C LC
MCA04940
Figure 17 Clock Generation Unit Block Diagram
Data Sheet
62
V2.3, 2003-11