TC11IB Datasheet, PDF (46/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
Table 2
TC11IB Block Address Map(cont’d)
Seg- Address
ment Range
Size Description
F000 0000_H – 1 MB
F00F FFFF_H
On-Chip Peripherals & Ports
F010 0000_H – 512 KB Reserved
F017 FFFF_H1)
F018 0000_H – 64 KB ComDRAM Control Registers
F018 FFFF_H
F019 0000_H – 2.4375 Reserved
F03F FFFF_H1) MB
F040 0000_H – 1 MB
F04F FFFF_H
PCI/FPI-Bridge Registers
F050 0000_H – ~11 MB Reserved
15 _{F0FF FFFFH}
F100 0000_H – 16 MB PCI Configuration Space
F1FF FFFF_H
F200 0000_H – 6 x 256 BCU0 and Fast Ethernet
F200 05FF_H B
Registers
F200 0600_H – ~94 MB Reserved
F7E0 FEFF_H
F7E0 FF00_H – 256 B CPU Slave Interface Registers
F7E0 FFFF_H
(CPS)
F7E1 0000_H – 64 KB Core SFRs
F7E1 FFFF_H
F7E2 0000_H – 15 x 128 Reserved
F7FF FFFF_H KB
F800 0000_H – 8 MB
F87F FFFF_H
LMB Peripheral Space
(EBU_LMB and local memory
eDRAM control registers)
F880 0000_H – 120 MB Reserved
FFFF FFFF_H
1) _{Any access to this area will result in unpredicted behaviors of PORTs.}
DMU PMU
Acc. Acc.
via via
S_FPI S_FPI
–
–
via via
S_FPI S_FPI
–
–
via
F_FPI
–
via
F_FPI
–
–
via
F_FPI
–
via
LMB
–
Note: Accesses to address defined as “Reserved” in Table 2 lead to a bus error. The
exceptions are marked with ¹⁾
Data Sheet
42
V2.3, 2003-11