TC11IB Datasheet, PDF (22/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
Table 1
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
RD
RD/WR
WAIT
SVM
ALE
RAS
CAS
Pin Definitions and Functions(cont’d)
Pin In PU/ Functions
Out PD¹⁾
EBU_LMB Address Bus Input / Output Lines
AA26 I/O PUC EBU_LMB Address Bus Line 0
V24 I/O PUC EBU_LMB Address Bus Line 1
W24 I/O PUC EBU_LMB Address Bus Line 2
Y24 I/O PUC EBU_LMB Address Bus Line 3
Y25 I/O PUC EBU_LMB Address Bus Line 4
AA25 I/O PUC EBU_LMB Address Bus Line 5
Y26 I/O PUC EBU_LMB Address Bus Line 6
W25 I/O PUC EBU_LMB Address Bus Line 7
W26 I/O PUC EBU_LMB Address Bus Line 8
V25 I/O PUC EBU_LMB Address Bus Line 9
V26 I/O PUC EBU_LMB Address Bus Line 10
U25 I/O PUC EBU_LMB Address Bus Line 11
U24 I/O PUC EBU_LMB Address Bus Line 12
U26 I/O PUC EBU_LMB Address Bus Line 13
T26 I/O PUC EBU_LMB Address Bus Line 14
T25 I/O PUC EBU_LMB Address Bus Line 15
T24 I/O PUC EBU_LMB Address Bus Line 16
R23 I/O PUC EBU_LMB Address Bus Line 17
R24 I/O PUC EBU_LMB Address Bus Line 18
R25 I/O PUC EBU_LMB Address Bus Line 19
A24 I/O PUC EBU_LMB Address Bus Line 20
B23 I/O PUC EBU_LMB Address Bus Line 21
C23 I/O PUC EBU_LMB Address Bus Line 22
D22 I/O PUC EBU_LMB Address Bus Line 23
AB26 I/O PUC EBU_LMB Read Control Line
Output in the master mode
Input in the slave mode.
N24 I/O PUC _{EBU_LMB Write Control Line}
Output in the master mode
Input in the slave mode.
C19 I/O PUC EBU_LMB Wait Control Line
D20 O PUB EBU_LMB Supervisor Mode Output
A20 O PDC EBU_LMB Address Latch Enable Output
P25 O PUC EBU_LMB SDRAM Row Address Strobe Output
N25 O PUC EBU_LMB SDRAM Column Address Strobe Output
Data Sheet
18
V2.3, 2003-11