TC11IB Datasheet, PDF (31/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
provides the ASC with a separate serial clock signal that can be very accurately adjusted
by a prescaler implemented as a fractional divider.
Features:
• Full duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baudrate from 3 MBaud to 0.71 Baud (@ 48 MHz clock)
• Multiprocessor mode for automatic address/data byte detection
• Loop-back capability
• Support for IrDA data transmission up to 115.2 KBaud maximum
• Half-duplex 8-bit synchronous operating mode
– Baudrate from 6 MBaud to 488.3 Baud (@ 48 MHz clock)
• Double buffered transmitter/receiver
• Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
• FIFO
– 8 bytes receive FIFO (RXFIFO)
– 8 bytes transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 9-bit FIFO data width
– Programmable Receive/Transmit Interrupt Trigger Level
– Receive and transmit FIFO filling level indication
– Overrun error generation
• Two pin pair RXD/TXD available at Port 1
Data Sheet
27
V2.3, 2003-11