TC11IB Datasheet, PDF (50/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
Protection for PTE based translation
Memory protection for addresses that undergo PTE based translation is enforced using
the PTE used for the address translation. The PTE provides support for protecting a
process from unauthorized read, write, or instruction fetches by other processes. The
PTE has the following bits that are provided for the purpose of protection:
l XE (Execute Enable) enables instruction fetch to the page.
l WE (Write Enable) enables data writes to the page.
l RE (Read Enable) enables data reads from the page.
Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual
address space are disallowed when operating in Virtual mode. In Physical mode, User-
0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual
address that is restricted to User-1 or Super-visor mode will cause a Virtual Address
Protection (VAP) Trap in both the Physical and Virtual modes.
Data Sheet
46
V2.3, 2003-11