TC11IB Datasheet, PDF (16/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
Table 1
Pin Definitions and Functions(cont’d)
Symbol Pin
NMI
B2
CFG0 K2
CFG1 K3
CFG2 J1
CFG3 J2
CPU
C2
CLK
TRST
AE8
TCK
AF7
TDI
AD9
TDO
AF8
TMS
AD8
OCDSE H2
BRKIN H3
BRKOUT J3
In PU/
Out PD¹⁾
I PUB
I PDC
I PDC
I PUC
I PUC
O PUC
Functions
Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
Operation Configuration Inputs
The configuration inputs define the boot options of the
TC11IB after a hardware-invoked reset operation.
Clock Output
I PDC JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
I PUC JTAG Module Clock Input
I PUC JTAG Module Serial Data Input
O  JTAG Module Serial Data Output
I PUC JTAG Module State Machine Control Input
I PUC OCDS Enable Input
A low level on this pin during power-on reset
(PORST = 0) enables the on-chip debug support
(OCDS). In addition, the level of this pin during power-
on reset determines the boot configuration.
I PUC OCDS Break Input
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
O
OCDS Break Output
A low level on this pin indicates that a programmable
OCDS event has occurred.
Data Sheet
12
V2.3, 2003-11