TC11IB Datasheet, PDF (40/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
RB as well as TB provides on-chip data buffering whereas DMUR and DMUT perform
data transfer from/to the shared memory.
Two interfaces are provided by the Ethernet Controller Module:
1. MII interface for connection of Ethernet PHYs via eighteen Input / Output lines
2. Master/slave FPI bus interface for connection to the on-chip system bus for data
transfer as well as configuration.
Features
• Media Independent Interface (MII) according to IEEE 802.3
• Support 10 or 100 Mbps MII-based Physical devices.
• Support Full Duplex Ethernet.
• Support data transfer between Ethernet Controller and COM-DRAM.
• Support data transfer between Ethernet Controller and SDRAM via EBU.
• 256 x 32 bit Receive buffer and Transmit buffer each.
• Support burst transfers up to 8 x 32 Byte.
Media Access Controller (MAC)
• 100/10-Mbps operations
• Full IEEE 802.3 compliance
• Station management signaling
• Large on-chip CAM (Content Addressable Memory)
• Full duplex mode
• 80-byte transmit FIFO
• 16-byte receive FIFO
• PAUSE Operation
• Flexible MAC Control Support
• Support Long Packet Mode and Short Packet Mode
• PAD generation
Media Independent Interface (MII)
• Media independence.
• Multi-vendor point of interoperability.
• Support connection of MAC layer and Physical (PHY) layer devices.
• Capable of supporting both 100 Mb/s and 10 Mb/s data rates.
• Data and delimiters are synchronous to clock references.
• Provides independent four bit wide transmit and receive data paths.
• Support connection of PHY layer and Station Management (STA) devices.
• Provides a simple management interface.
• Capable of driving a limited length of shielded cable.
Data Sheet
36
V2.3, 2003-11